Communications of the ACM
Testing Unbuilt Chips
Credit: MIT
Massachusetts Institute of Technology (MIT) researchers have developed Hornet, a software simulator they say models the performance of multicore chips much more accurately than its predecessors.
The researchers recently developed a new version of the simulator that factors in power consumption, patterns of communication between cores, the processing times of individual tasks, and memory-access patterns. Hornet is designed to complement, not compete with, more traditional approaches for analyzing chip performance, says MIT Ph.D. student Myong Hyon Cho.
The different tasks performed by a chip's components are synchronized by a master clock, and during each clock cycle every component performs one task. The researchers note that Hornet is much slower than its predecessors, but it can provide a "cycle-accurate" simulation of a chip with 1,000 cores. "'Cycle-accurate' means the results are precise to the level of a single cycle," Cho says.
Hornet could have advantages in situations in which "you want to test out several ideas quickly, with good accuracy," says Cornell University professor Edward Suh.
From MIT News
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