Massachusetts Institute of Technology (MIT) researchers have developed a high-efficiency video coding (HEVC) chip, which demonstrates that implementing HEVC algorithms in silicon chips is possible and shows how its design principles could be used.
The HEVC standard exploits the fact that in successive frames of video, most of the pixels stay the same. MIT's chip increases efficiency by pipelining the decoding process. A chunk of data is decompressed and passed to a motion-compensation circuit, but as soon as the motion compensation begins, the decompression circuit takes in the next chunk of data. After motion compensation is complete, the data passes to a circuit that applies the corrective data and, finally, to a filtering circuit that smooths out whatever rough edges remain. The application of the corrective data is a single calculation known as matrix multiplication.
The researchers also developed a more efficient way to store video data in memory, which involves optimizing the data into small square blocks that are stored together.
"When you access something from memory, you not only get the pixels on the right and left, but you also get the pixels on the top and bottom in the same request," says MIT's Chiraag Juvekar.
From MIT News
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