The European Union is funding a project that seeks to improve the reliability of terascale computing by improving chip design.
The researchers involved in the Terascale Reliable Adaptive Memory Systems project have conducted in-depth variability and reliability analyses to develop chip circuits that are much less prone to errors. The circuits feature new designs that yield reliable memory systems from currently unreliable nanodevices. The researchers say terascale computing is key to shrinking devices, and it involves ultrafast technology supported by single microchips that can perform trillions of operations per second.
Terascale technology could enable semiconductors commonly used to make integrated circuits for all kinds of appliances to measure less than 10 nanometers within several years. The main challenge for the team was to develop reliable, energy efficient, and cost-effective computing using new technologies with individual transistors potentially measuring below five nanometers in size.
The team investigated carbon nanotubes, new transistor geometries, and state-of-the-art nanowires. They also employed models to analyze reliability, from the technology to the circuit level. Their innovations could redefine modern standard complementary metal-oxide semiconductors (CMOS), and help European chipmakers fabricate CMOS devices below the 16 nm range.
From CORDIS News
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