Communications of the ACM
Tool Checks Computer Architectures, Reveals Flaws in Emerging Design
Researchers testing a new system to analyze memory operations across any computer architecture discovered a series of errors in the RISC-V instruction specification.
Credit: Hexus.net
Researchers at Princeton University have discovered a series of errors in the RISC-V instruction specification that are now leading to changes in the new system.
The RISC-V project aims to facilitate open source design for computer chips, offering the possibility of opening up chip designs beyond the few companies dominating the industry.
The researchers, testing a technique they created for analyzing computer memory use, found more than 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. If uncorrected, the problems could cause errors in software running on RISC-V chips.
The researchers discovered the problems when testing their new TriCheck system to analyze memory operations across any computer architecture.
The researchers described the TriCheck system in a paper presented this week at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2017) in China.
From Princeton University
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