Communications of the ACM
Software Is Crammed Full of Bugs. This 'Exciting' Project Could Banish Most of Them
Arm says Morello serves as a real-world test platform for deployment of more secure hardware architecture in processors of the future. It uses the Capability Hardware Enhanced RISC Instructions (CHERI) architecture to extend conventional hardware ISAs wit
Credit: Arm
Chip designer Arm has released a prototype development board based on the Capability Hardware Enhanced RISC Instructions (CHERI) architecture.
The Morello board, developed with researchers at the U.K.’s University of Cambridge and Microsoft, among others, could pave the way for new CPU designs that eliminate memory-related security flaws stemming from code written in programming languages like C and C++.
Google's Ben Laurie said CHERI's software compartmentalization is similar to process isolation in software for current operating systems.
Said Microsoft's Saar Amar, "There are billions of lines of C and C++ code in widespread use, and CHERI's strong source-level compatibility provides a path to achieving the goals of high-performance memory safety without requiring a ground-up rewrite."
From ZDNet
View Full Article
Abstracts Copyright © 2022 SmithBucklin, Washington, DC, USA
No entries found