Communications of the ACM
Growing Europe's Nanowires
Credit: ICT Results
European researchers engaged in the NODE project have devised a cutting-edge technology for "growing" nanowires in a vertical configuration, which could lead to faster, smaller microchips designed to satisfy integrated circuit performance requirements for the next decade.
The bottom-up nanowire growth process introduces fewer defects, and NODE project coordinator Lars Samuelson speculates that "this vertical arrangement may be the route to [three-dimensional] circuit design as well as to realize monolithic on-chip optoelectronics." NODE concentrated on silicon-indium arsenide and silicon-silicon germanium blends. "One of the breakthroughs was the . . . perfect deposition of high-K dielectrics coating the nanowires and serving as a dielectric in the wrap-gate transistors," Samuelson says. "We developed a very good technique for this."
High-K dielectrics surmount some of the restrictions of silicon dioxide at extremely small scales and hold promise as an approach for further miniaturizing integrated circuits. "This technology is not ready for industrial applications, and whether it will be three, six, or nine years before it appears industrially, I cannot say," cautions Samuelson. "But we established the state of the art, we have the best results."
From ICT Results
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